Auto-Arch Tournament
An AI agent loop that redesigns your RISC-V CPU and formally proves every win
The Panel's Take
Auto-Arch Tournament is an autonomous research system where an AI agent iteratively proposes, implements, and validates microarchitectural improvements to a RISC-V CPU. Starting from a standard 5-stage pipeline, the loop runs hypotheses in parallel, each going through formal verification (53 symbolic checks), cycle-accurate simulation, multi-seed FPGA place-and-route, and CoreMark CRC validation. Only hypotheses that beat the current champion get merged; everything else gets discarded. Starting from 301 iterations/second, the system hit 577 iter/s (+92%) across 73 attempts in 9.8 hours — producing a design 26% faster and 40% smaller in LUTs than the baseline. The insight the author drives home is that the real innovation isn't the AI agent — it's the verifier. The orchestrator is hardcoded to prevent agents from manipulating their own evaluation gates, a simple but critical design constraint that turns a creative process into a trustworthy one. Without a rigorous verification harness, agent-driven optimization becomes a confidence trick. This is early but fascinating proof that AI-driven hardware design loops can produce commercially meaningful gains. The repo uses Claude Code or Codex as the coding agent, SystemVerilog for the RTL, and standard open-source EDA tooling (Yosys, nextpnr, Verilator). It's a compelling template for anyone building agentic optimization loops where correctness matters.
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Auto-Arch Tournament verdict: SHIP 🚀 3 ships · 1 skip from the expert panel Full review: shiporskip.io/tool/auto-arch-tournament-fesens-ai-agent-cpu-design-riscv-2026
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“The hardcoded orchestrator pattern is the real take-home here. Building AI loops that can't game their own eval is a solved problem when you just... don't give the agent write access to the evaluator. Obvious in hindsight, rarely implemented.”
“63 out of 73 proposals failed. That's an 86% failure rate and heavy use of API credits on a narrow RISC-V benchmark. Impressive for a demo but the economics don't work yet for serious chip design at scale.”
“AI-driven hardware design is going to collapse the chip design cycle from years to weeks. This is a primitive ancestor of the tools that will design the next generation of AI accelerators.”
“The blog post that comes with this repo is one of the best pieces of technical writing I've seen in months. The transparency about failure rates and the verifier insight make it genuinely educational.”